wv3hg264m72eeu-d6 january 2006 rev. 0 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 1gb C 2x64mx72 ddr2 sdram unbuffered description the wv3hg264m72eeu is a 2x64mx74 double data rate ddr2 sdram high density module. this memory module consists of eighteen 64mx8 bit with 4 banks ddr2 synchronous drams in fbga packages, mounted on a 240-pin dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option features 240-pin, dual in-line memory module (dimm) fast data transfer rates: pc2-6400*, pc2-5300*, pc2-4200 and pc2-3200 utilizes 800*, 667*, 533 and 400 mt/s ddr2 sdram components v cc = v ccq = 1.8v 0.1v jedec standard 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option four-bit prefetch architecture programmable cas# latency (cl): 3, 4, 5 and 6 on-die termination (odt) serial presence detect (spd) with eeprom gold edge contacts dual rank rohs compliant package ? 240 pin dimm: 30.00mm (1.181") typ operating frequencies pc2-3200 pc2-4200 pc2-5300* pc2-6400* clock speed 200mhz 266mhz 333mhz 400mhz cl-t rcd -t rp 3-3-3 4-4-4 5-5-5 6-6-6 * consult factory for availability
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin configuration pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1v ref 61 a4 121 v ss 181 v ccq 2v ss 62 v ccq 122 dq4 182 a3 3 dq0 63 a2 123 dq5 183 a1 4 dq1 64 v cc 124 v ss 184 v cc 5v ss 65 v ss 125 dm0 185 ck0 6 dqs0# 66 v ss 126 nc 186 ck0# 7dqs067 v cc 127 v ss 187 v cc 8v ss 68 nc 128 dq6 188 a0 9dq269v cc 129 dq7 189 v cc 10 dq3 70 a10/ap 130 v ss 190 ba1 11 v ss 71 ba0 131 dq12 191 v ccq 12 dq8 72 v ccq 132 dq13 192 ras# 13 dq9 73 we# 133 v ss 193 cs0# 14 v ss 74 cas# 134 dm1 194 v ccq 15 dqs1# 75 v ccq 135 nc 195 odt0 16 dqs1 76 cs1# 136 v ss 196 a13 17 v ss 77 odt1 137 ck1 197 v cc 18 nc 78 v ccq 138 ck1# 198 v ss 19 nc 79 v ss 139 v ss 199 dq36 20 v ss 80 dq32 140 dq14 200 dq37 21 dq10 81 dq33 141 dq15 201 v ss 22 dq11 82 v ss 142 v ss 202 dm4 23 v ss 83 dqs4# 143 dq20 203 nc 24 dq16 84 dqs4 144 dq21 204 v ss 25 dq17 85 v ss 145 v ss 205 dq38 26 v ss 86 dq34 146 dm2 206 dq39 27 dqs2# 87 dq35 147 nc 207 v ss 28 dqs2 88 v ss 148 v ss 208 dq44 29 v ss 89 dq40 149 dq22 209 dq45 30 dq18 90 dq41 150 dq23 210 v ss 31 dq19 91 v ss 151 v ss 211 dm5 32 v ss 92 dqs5# 152 dq28 212 nc 33 dq24 93 dqs5 153 dq29 213 v ss 34 dq25 94 v ss 154 v ss 214 dq46 35 v ss 95 dq42 155 dm3 215 dq47 36 dqs3# 96 dq43 156 nc 216 v ss 37 dqs3 97 v ss 157 v ss 217 dq52 38 v ss 98 dq48 158 dq30 218 dq53 39 dq26 99 dq49 159 dq31 219 v ss 40 dq27 100 v ss 160 v ss 220 ck2 41 v ss 101 sa2 161 cb4 221 ck2# 42 cb0 102 nc 162 cb5 222 v ss 43 cb1 103 v ss 163 v ss 223 dm6 44 v ss 104 dqs6# 164 dm8 224 nc 45 dqs8# 105 dqs6 165 nc 225 v ss 46 dqs8 106 v ss 166 v ss 226 dq54 47 v ss 107 dq50 167 cb6 227 dq55 48 cb2 108 dq51 168 cb7 228 v ss 49 cb3 109 v ss 169 v ss 229 dq60 50 v ss 110 dq56 170 v ccq 230 dq61 51 v ccq 111 dq57 171 cke1 231 v ss 52 cke0 112 v ss 172 v cc 232 dm7 53 v cc 113 dqs7# 173 nc 233 nc 54 nc 114 dqs7 174 nc 234 v ss 55 nc 115 v ss 175 v ccq 235 dq62 56 v ccq 116 dq58 176 a12 236 dq63 57 a11 117 dq59 177 a9 237 v ss 58 a7 118 v ss 178 v cc 238 v ccspd 59 v cc 119 sda 179 a8 239 sa0 60 a5 120 scl 180 a6 240 sa1 pin names pin name function a0-a13 address input ba0, ba1 bank address dq0 ~ dq63 data input/output cb0-cb7 check bits dqs0 ~ dqs8 data strobe dqs0# ~ dqs8# data strobe negative odt0, odt1 on die termination ck0,ck0# - ck2, ck2# clock input cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable v cc voltage supply (1.8v0.1v) v ccq i/o power (1.8v) v ss ground sa0 ~ sa2 spd address sda serial data i/o scl serial clock dm(0-8) data masks a10/ap address input/auto precharge v ref i/o reference supply v ccspd serial eeprom nc no connect
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram a0 a1 a2 sa0 sa1 sa2 scl sda wp v ccspd v cc /v ccq v ref v ss serial pd ddr2 sdrams ddr2 sdrams ddr2 sdrams dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm/ rdqs cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs1# cs0# dqs0 dqs0# dm0 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs4 dqs4# dm4 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs1 dqs1# dm1 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs5 dqs5# dm5 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs2 dqs2# dm2 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs6 dqs6# dm6 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs3 dqs3# dm3 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs7 dqs7# dm7 cs0# cs1# ba0 - ba1 a0 - a13 ras# cas# we# cke0 cke1 odt0 odt1 cs0# : ddr2 sdrams cs1# : ddr2 sdrams ba0 - rba1 : ddr2 sdrams a0 - a13 : ddr2 sdrams ras# : ddr2 sdrams cas# : ddr2 sdrams we# : ddr2 sdrams cke0 : ddr2 sdrams cke1 : ddr2 sdrams odt0 : ddr2 sdrams odt1 : ddr2 sdrams dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# a0 wp a1 a2 serial pd *clock wiring *wire per clock loading table/wiring diagrams notes: 1. dq, dm, dqs, dqs# resistors: 5.1 ohms +/- 5% 2. bax, ax, ras#, cas#, we# resistors: 5.1 ohms +/- 5% clock input ddr2 sdrams *ck0/ck0# *ck1/ck1# *ck2/ck2# 6 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams note: all resistor values are 22 ohms unless otherwise speci? ed.
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs dc operating conditions all voltages referenced to v ss parameter symbol rating units notes min. type max. supply voltage v cc 1.7 1.8 1.9 v 1 i/o supply voltage v ccq 1.7 1.8 1.9 v 4 vccl supply voltage v ccl 1.7 1.8 1.9 v 4 i/o reference voltage v ref 0.49*v ccq 0.50*v ccq 0.51*v ccq v2 i/o termination voltage v tt v ref -0.04 v ref v ref +0.04 v 3 notes: 1. v cc and v ccq must track each other. v ccq must be less than or equal to v cc . 2. v ref is expected to equal v ccq/2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed +/- percent of the dc value. peak-to-peak ac noise on v ref may not exceed +/-2 percent of v ref . this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 4. v ccq tracks with v cc ; v ccl track with v cc . absolute maximum ratings sstl_1.8v symbol parameter min max unit v cc voltage on v cc pin relative to v ss - 1.0 2.3 v v ccq voltage on v ccq pin relative to v ss - 0.5 2.3 v v ccl voltage on v ccl pin relative to v ss - 0.5 2.3 v v in , v out voltage on any pin relative to v ss - 0.5 2.3 v t stg storage temperature -55 100 c t case device operating temperature 0 85 c i l input leakage current; any input 0v wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs operating temperature condition parameter symbol rating units notes operating temperature toper 0oc to 85oc oc 1, 2 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, p lease refer to jedec jesd51.2. 2. at 0 - 85 oc, operation temperature range, all dram speci? cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih(dc) vref + 0.125 vref + 0.300 v input low (logic 0) voltage v il(dc) -0.300 vref - 0.125 v input ac logic level all voltages referenced to v ss parameter symbol min max units ac input high (logic 1) voltage v ih(ac) vref+ 0.250 v ac input low (logic 0) voltage ddr2-400 & ddr2-533 v il(ac) - vref - 0.250 v ac input low (logic 0) voltage ddr2-667, ddr2-800 (tbd) v il(ac) - vref - 0.200 v capacitance t a = 25c, f = 1mhz, v cc = v ccq = 1.8v parameter symbol min max units input capacitance: (a0 ~ a13 , ba0 ~ ba1, ras#, cas#, we#) c in1 22 40 pf input capacitance: (cke0, cke1), (odt0, odt1) c in2 13 22 pf input capacitance: (cs0#, cs1#) c in3 13 22 pf input capacitance: (ck0, ck0# ~ ck2, ck2#) c in4 10 16 pf input capacitance: (dm0 ~ dm8), (dqs0-dqs8) c in6 (e6) 911pf c in6 (d5) 912pf input capacitance: (dq0 ~ dq63), (cb0-cb7) c out1 (e6) 911pf c out1 (d5) 912pf
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 i cc specifications and conditions symbol proposed conditions 806 665 534 403 units i cc0* operating one bank active-precharge current; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 837 792 792 ma i cc1* operating one bank active-read-precharge current; i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min (i cc ), t rcd = t rcd (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc4w tbd 972 972 972 ma i cc2p** precharge power-down current; all banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd 144 144 144 ma i cc2q** precharge quiet standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating tbd 630 540 540 ma i cc2n** precharge standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching tbd 720 630 630 ma i cc3p** active power-down current; all banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 tbd 540 540 540 ma slow pdn exit mrs(12) = 1 tbd 216 216 216 ma i cc3n** active standby current; all banks open; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min (i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 990 900 900 ma i cc4w** operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max (i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1332 1152 1062 ma i cc4r* operating burst read current; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max (i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc4w tbd 1377 1197 1062 ma i cc5b** burst auto refresh current; t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 2700 2520 2520 ma i cc6* self refresh current; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal tbd 144 144 144 ma i cc7* operating bank interleave read current; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = t rc d(i cc )-1*t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = 1*t ck (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching. tbd 2052 2052 2052 ma * value calculated as one module rank in thes operating condition, and all other module ranks in
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit clock clock cycle time cl = 6 t ck (6) tbd tbd ps cl = 5 t ck (5) tbd tbd 3000 8000 ps cl = 4 t ck (4) tbd tbd 3750 8000 3,750 8,000 5,000 8,000 ps cl = 3 t ck (3) tbd tbd 5000 8000 5,000 8,000 5,000 8,000 ps ck high-level width t ch tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck half clock period t hp tbd tbd min (t ch , t cl ) min (t ch , t cl ) min (t ch , t cl ) ps data dq output access time from ck/ck# t ac tbd tbd -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz tbd tbd t ac (max) t ac (max) t ac (max) ps data-out low-impedance window from ck/ck# t lz tbd tbd t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) ps dq and dm input setup time relative to dqs t ds tbd tbd 100 100 150 ps dq and dm input hold time relative to dqs t dh tbd tbd 225 225 275 ps a dq and dm input pulse width (for each input) t dipw tbd tbd 0.35 0.35 0.35 t ck data hold skew factor t qhs tbd tbd 340 400 450 ps dqdqs hold, dqs to ? rst dq to go nonvalid, per access t qh tbd tbd t hp - t qhs t hp - t qhs t hp - t qhs ps data valid output window (dvw) t dvw tbd tbd t qh - t dqsq t qh - t dqsq t qh - t dqsq ns data strobe dqs input high pulse width t dqsh tbd tbd 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl tbd tbd 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck tbd tbd -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck rising setup time t dss tbd tbd 0.2 0.2 0.2 t ck dqs falling edge from ck rising hold time t dsh tbd tbd 0.2 0.2 0.2 t ck dqsdq skew, dqs to last dq valid, per group, per access t dqsq tbd tbd 240 300 350 ps dqs read preamble t rpre tbd tbd 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs write preamble setup time t wpres tbd tbd 000ps dqs write preamble t wpre tbd tbd 0.35 0.35 0.35 t ck dqs write postamble t wpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck write command to ? rst dqs latching transition t dqss tbd tbd wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck address and control input pulse width for each input t ipw tbd tbd 0.6 0.6 0.6 t ck note: ? ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different. continued on next page
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters (cont'd) 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit command and address address and control input setup time t is tbd tbd 200 250 250 ps address and control input hold time t ih tbd tbd 275 375 475 ps cas# to cas# command delay t ccd tbd tbd 222t ck active to active (same bank) command t rc tbd tbd 55 55 55 ns active bank a to active bank b command t rrd tbd tbd 7.5 7.5 7.5 ns active to read or write delay t rcd tbd tbd 15 15 15 ns four bank activate period t faw tbd tbd 37.5 37.5 37.5 37.5 37.5 37.5 active to precharge command t ras tbd tbd 45 70,000 45 70,000 45 70,000 ns internal read to precharge command delay t rtp tbd tbd 7.5 7.5 7.5 ns write recovery time t wr tbd tbd 15 15 15 ns auto precharge write recovery + precharge time t dal tbd tbd t wr + t rp t wr + t rp t wr + t rp ns internal write to read command delay t wtr tbd tbd 10 7.5 10 ns precharge command period t rp tbd tbd 15 15 15 precharge all command period t rpa tbd tbd t wr + t ck t wr + t ck t wr + t ck ns load mode command cycle time t mrd tbd tbd 222t ck cke low to ck,ck# uncertainty t delay tbd tbd t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih ns refresh refresh to refresh command interval t rfc tbd tbd 127.5 70,000 127.5 70,000 127.5 70,000 ns average periodic refresh interval t refi tbd tbd 7.8 7.8 7.8 s self refresh exit self refresh to non-read command t xsnr tbd tbd t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd tbd tbd 200 200 200 t ck exit self refresh timing reference t isxr tbd tbd t is t is t is ps odt odt turn-on delay t aond tbd tbd 222222t ck odt turn-on t aon tbd tbd t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 ps odt turn-off delay t aofd tbd tbd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof tbd tbd t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn-on (power-down mode) t aonpd tbd tbd t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power-down mode) t aofpd tbd tbd t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 ps odt to power-down entry latency t anpd tbd tbd 333t ck odt power-down exit latency t axpd tbd tbd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard tbd tbd 2 22t ck exit active power-down to read command, mr[bit12=1] t xards tbd tbd 7-al 6 - al 6 - al t ck a exit precharge power-down to any non-read command. t xp tbd tbd 2 22t ck cke minimum high/low time t cke tbd tbd 333t ck note: ? ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different.
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 133.35 (5.25) 133.20 (5.244) 10.00 (0.394) typ 17.80 (0.700) typ 30.50 (1.201) 29.85 (1.175) 63.00 (2.48) typ 55.00 (2.165) typ 3.00 (0.118) (4x) 4.00 (0.158) (4x) 2.50 0.20 (0.098 0.007) 1.50 0.10 (0.059 0.004) 4.00 (0.158) 5.00 (0.196) 1.00 (0.039) typ 0.80 0.05 (0.032 0.002) typ pin 20 pin 1 0.054 (1.37) 0.046 (1.17) 0.158 (4.00) max front view back view + + pin 1 pin 121 package dimensions for d6 * all dimensions are in millimeters and (inches) ordering information for d6 part number clock/data rate frequency cas latency t rcd t rp height* w3hg264m72eeu806d6xg** 400mhz/800mb/s 6 6 6 30.00mm (1.181") typ w3hg264m72eeu665d6xg** 333mhz/667mb/s 5 5 5 30.00mm (1.181") typ w3hg264m72eeu534d6xg 266mhz/533mb/s 4 4 4 30.00mm (1.181") typ w3hg264m72eeu403d6xg 200mhz/400mb/s 3 3 3 30.00mm (1.181") typ ** consult factory for availability notes: ? rohs compliant product. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory component source control. the place holder for this is shown as a l ower case "x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali? ed sourcing options. (g = in? neon, m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide wv 3 h g 2 64m 72 e e u xxx d6 x g wedc memory (sdram) ddr 2 gold dual rank depth bus width component width x8 1.8v unbuffered speed (mb/s) package 240 pin component vendor name (g = in? neon) (m = micron) (s = samsung) g = rohs compliant
wv3hg264m72eeu-d6 january 2006 rev. 0 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 1gb C 2x64mx72 ddr2 sdram unbuffered revision history rev # history release date status rev 0 created january 2006 advanced
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